In the semiconductor industry, minimization of the feature size of MOS transistors in integrated circuits is a common goal. This goal is essentially driven by the need to produce integrated circuits at ever-lower costs, while improving circuit functionality and speed. Such downscaling can be achieved by reducing the characteristic dimensions of the transistors, i.e. reducing the gate lengths, the gate oxide thickness, and the junction depths, and by increasing the channel doping levels. However, scaled-down MOS transistors generally suffer from a phenomenon referred to as the “short-channel effect”. The short-channel effect has an adverse impact on the switching performance of the transistors, because such switching is inefficiently controlled by the gate electrode, which leads to an undesired decrease in the threshold voltage. Mechanically, the depletion regions around the source and the drain occupy an increasingly large fraction of the channel region, so that a lower potential on the gate is needed to achieve inversion in the channel.
Referring to the FIG. 1, a conventional scaled-down MOS transistor 100, which is fabricated within a semiconductor substrate 102, includes a source extension region 106a and a drain extension region 106b. The source extension region 106a and the drain extension region 106b have shallow junctions in order to minimize the short-channel effect that occurs in MOS transistors having sub-micron or nanometer dimensions. The MOS transistor 100 further includes a source region 108a and a drain region 108b that have deeper junctions, relative to the source extension region 106a and the drain extension region 106b, to provide lower resistance. The MOS transistor 100 also includes a gate structure 110, which is comprised of a gate dielectric 112 and a gate electrode 114. An insulative spacer 118, which is typically comprised of silicon nitride (SiN), is disposed on the sidewalls of the gate structure 110. The MOS transistor 100 further includes silicide regions 120a, 120b, and 120c to provide low-resistance electrical contact with the source/drain 106a/106b and the gate electrode 114. The MOS transistor is electrically isolated from other devices by shallow trench isolation structures 104.
A problem lies in that impurities in the source/drain extension regions 106a/106b tend to diffuse to the region immediately under the gate 110. The portions of the source/drain extension regions 106a/106b formed immediately under the gate 110 have a higher electric resistance relative to the portions of the extension regions 106a/106b located immediately under the sidewall spacers 118. For this reason, the transistor 100 has effective resistances R that are connected in series to the source and the drain. This inhibits the flow of electric current, thus decreasing operation speed.
A second problem concerns the rise of channel dopant concentration, which in turn causes a rise in threshold voltage in the field effect transistor. In order to meet miniaturization requirements in MOS transistors, the impurity concentration of the channel impurity region is necessarily raised. At the same time, contemporary semiconductor devices are designed to operate with a lower power supply voltage, such as ranging from 5V to 3.3V. For operation with such a low power supply voltage, the threshold voltage of the field effect transistor needs to be lower. For this reason, any rise in the threshold voltage of MOS transistor due to the rise in channel dopant concentration is undesirable. On the other hand, a channel doping level that is too high in scaled-down devices gives rise to superfluous leakage current and junction breakdown.
In an attempt to overcome the stated disadvantages, elevated source and drain structures have been suggested. Referring to FIG. 2, a gate structure 210 comprised of a gate dielectric 212 and a gate electrode 214 is formed on the surface of the semiconductor substrate 202. A source extension region 206a and a drain extension region 206b are then formed in the semiconductor substrate. A spacer 218, typically comprised of silicon nitride (SiN), is formed on the sidewalls of the gate structure 210. An epitaxial layer 205, typically comprised of silicon, is grown on the exposed portions of the source/drain extension regions 206a/206b, typically using selective epitaxial growth. Following the growth of the epitaxial layer 205, dopants are implanted and activated to form an elevated source 208a and an elevated drain 208b. The MOS transistor 200 further includes silicide regions 220a, 220b, and 220c to provide electrical contacts to the elevated source/drain regions 208a/208b and the gate electrode 214.
A MOS transistor having an elevated source/drain produced according to the structure of FIG. 2 is effective for reducing the resistance of the source and drain regions by increasing the thickness and the doping level by elevating the source/drain regions 208a/208b. However, it is inevitable that the dopants of the source/drain extension regions 206a/206b diffuse into the region immediately under the gate 210, which result in junction leakage current through the source/drain extension regions 206a/206b. 